Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that uses magnetic elements. For example, Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter). STT-MRAM is also known as Spin Transfer Torque RAM (STT-RAM), Spin Torque Transfer Magnetization Switching RAM (Spin-RAM), and Spin Momentum Transfer (SMT-RAM).
FIG. 1 illustrates a conventional STT-MRAM bit cell 1000. The STT-MRAM bit cell 1000 includes magnetic tunnel junction (MTJ) storage element 1050, a transistor 1100, a bit line 1200 and a word line 1300. The MTJ storage element is formed, for example, from a pinned layer and a free layer, each of which can hold a magnetic field or polarization, separated by an insulating (tunneling barrier) layer as illustrated in FIG. 1. The polarization of the free layer can be reversed so that the polarity of the pinned layer and the free layer are either substantially aligned or opposite. The resistance of the electrical path through the MTJ will vary depending on the alignment of the polarizations of the pinned and free layers. This variance in resistance can be used to program and read the bit cell 1000, as is known. The STT-MRAM bit cell 1000 also includes a source line 1400, a sense amplifier 1500, read/write circuitry 1600 and a bit line reference 1700. Those skilled in the art will appreciate the operation and construction of the memory cell 1000 is known in the art. Additional details concerning such memory cells are provided, for example, in M. Hosomi, et al., “A Novel Nonvolatile Memory with Spin Transfer Torque Magnetoresistive Magnetization Switching: Spin-RAM,” Proceedings of IEDM Conference (2005), which is incorporated herein by reference in its entirety.
With reference to FIGS. 2(a)-(c), conventional MTJ storage elements generally are formed by first patterning a bottom fixed layer, forming a single damascene, depositing the tunneling barrier/free layer/top electrode stack, and performing a chemical mechanical polishing (CMP) step.
For example, as shown in FIG. 3, conventional MTJ storage elements generally are formed by depositing an MTJ and hardmask layer stack on the top metal layer (e.g., M3) of a metal stack (e.g., interconnect 40) using physical vapor deposition (PVD). The MTJ and hardmask layer stack commonly includes a bottom electrode layer 50 which may be formed, for example, from tantalum, a pinned layer 60, a tunneling barrier layer 90, a free layer 100, and a hardmask or upper electrode layer 110 which may be formed for example, from Ta/TaN or Ti/TiN.
In the conventional methods, a first step commonly includes depositing the bottom electrode layer 50 (e.g., Ta), the pinned layer 60, the tunneling barrier 90, the free layer 100, and the hardmask layer (Ta/TaN, Ti/TN). The pinned layer 60 may include one or more layers or films (e.g., a pinned layer stack). Next, the MTJ stack is subjected to a magnetic annealing process in a vacuum. A pattern is then applied to the MTJ stack using a lithography technique. The patterned cell size may be larger than the final size. Each of the aforementioned layers can be comprised of one or more layers or films.
Next, the MTJ stack is etched. The etching process includes trimming the resist size and pattern hardmask, stripping the resist, etching the free layer 100, and etching the pinned layer 60 and the bottom electrode layer 50. The MTJ stack is then cleaned. The cleaning process commonly is compatible with low-k and MTJ cleaning. Next, a passivation layer is deposited to protect the MTJ storage element and the inter-layer dielectric 70. A combination stack may be needed, along with a low deposition temperature to protect the MTJ and promote adhesion between the MTJ and ILD. Finally, the MTJ and ILD are polished using a less aggressive chemical mechanical polishing (CMP) to prevent delaminating.
As shown in FIG. 3, the conventional STT-MRAM bit cell formed according to the conventional methods includes a substrate 10, word lines 20, and a contact 30 to VSS (not shown). The bottom electrode layer 50 is formed on the top metal layer of the interconnect 40. The pinned layer 60, the tunneling barrier layer 90, the free layer 100, and the top electrode 110 are formed on the bottom electrode layer 50. The ILD layer 70 is formed over the MTJ cell.